The present invention relates to semiconductor devices and more particularly, to a low power wake-up architecture for system on a chip (SOC) semiconductor devices including SOC circuitry designed for use with multiple package types and packages employing various pin counts.
Microcontroller units (MCUs) such as those used in SOCs typically have a low power mode including power gating for a major part of a core of the SOC. To exit from the low power mode, typically an external wakeup source provides a wake-up signal to the SOC through input/output (I/O) pads of the SOC. The I/O pads include I/O buffers for driving loads and/or to provide isolation against external shocks such as electrostatic discharge (ESD).
FIG. 1 shows a conventional buffer circuit 10 associated with an I/O pad (not shown) that has an input buffer 11 that receives an input signal from the I/O pad and generates a wakeup path signal (Ipp_ind). An input signal (Ipp_do) to the buffer circuit 10 is routed through an output buffer or driver 12. The buffer circuit 10 also receives a power on reset (POR) signal. However, this POR signal is separate from a general POR signal and this separate POR signal is provided to the buffer circuits connected to chip wakeup circuitry. This separate POR signal is inactive in low power mode.
The output buffer 12 may be disabled in low power mode, but input buffer 11 remains enabled by keeping the core supply to the input buffer 11 active to enable the wakeup path, which is shown as “core supply ON” input to the buffer circuit 10. In order to function, an IO supply to the buffer circuit 10 also is ON, shown as “IO supply ON”. However, keeping the input buffer 11 active adds significant power overhead that can use an extra 5-10 μA of current in a large circuit.
The requirement to provide the core supply to input buffers while in low power mode also presents a physical design overhead since an always ON power supply must be routed to selected pads/buffers. To minimize risk of shorting and avoid current leakage the layout and design of power supplies for pads/buffers should be separated from power supplies that may be OFF in low power mode. However this requirement increases complexity of the pad ring since a separate supply rail is needed to supply these pads/buffers. Customized glue logic may also be required for different pad ring components. Further, such custom logic requirements may not be available for circuits designed using a generic I/O library.
Therefore, it would be desirable to have a low power architecture for a semiconductor device that does not need to maintain I/O pads in an always ON state. It further would be desirable to be able to remove the requirement of providing a core power supply to the I/O pads.